搜索资源列表
VerilogfoFPGAbasedSDRAMController
- 使用Verilog实现基于FPGA的SDRAM控制器-The use of Verilog for FPGA-based SDRAM Controller
hssdrc_latest
- SDRAM 控制器 Verilog实现，很有借鉴意义。-SDRAM controller core Verilog implementation。With good referential significance.
webCam-FPGA
- 使用Verilog控制美光CMOS图像处理器，并转存到SDRAM中。使用FPGA为QL的带fuse系列-Control the use of Verilog Micron CMOS image processor and SDRAM in转存到. FPGA for use with QL series fuse
Xil3SD1800A_MIG_simplifiedUI_vlog_v92
- verilog 实现的spartan 3A dsp start kit DDR2 SDRAM 控制器-verilog achieved spartan 3A dsp start kit DDR2 SDRAM controller
sdram_verilog
- sdram的使用，使用verilog HDL来实现对sdram的操作！对时序和语言功底有要求！-sdram use verilog HDL used to achieve operation of the sdram! On the timing and language skills required!
SDRAM_controler_code
- SDRAM的verilog控制器代码极其仿真模块-The verilog code for SDRAM controller is extremely Simulation Module
ddr_verilog_xilinx
- xilinx的ddr sdram控制器文档-xilinx of ddr sdram controller documentation
mt48lc4m32b2.v
- SDRAM VHDL/Verilog simulation model
sdram_vhd_134
- This code is a SDRAM Controller IP Core for FPGA to interface with SDRAM Memory. This code is Verilog. This code is based Xilinx FPGA Playform.
c_xapp260
- xilinx应用指南xapp260的中文翻译版本。利用 Xilinx FPGA 和存储器接口生成器简化存储器接口。本白皮书讨论各种存储器接口控制器设计所面临的挑战和 Xilinx 的解决方案，同时也说明如何使用 Xilinx软件工具和经过硬件验证的参考设计来为您自己的应用（从低成本的 DDR SDRAM 应用到像 667 Mb/sDDR2 SDRAM 这样的更高性能接口）设计完整的存储器接口解决方案。-The use of Xilinx FPGA and Memory Interface Gen
median
- 中值滤波的实现，该代码使用的是verilog 语言 module median(clk,reset,load,din,mult,dout,over,a3,b3,c3,a2,b2,c2,a1,b1,c1)-Median filter implementation, the code using verilog language module median (clk, reset, load, din, mult, dout, over, a3, b3, c3, a2, b2, c2, a1,
I2C_v
- 对sdram的仿真程序，对sdram的仿真程对sdram的仿真程序序，-sdram
ddr-sdram--chengxu
- ddr的控制程序，实用Verilog语言实现的非常的具体，非常无奈过的实用。-ddr
verilog_k4s643232h_0401
- Samsung SDRAM Simulation Verilog
sdram
- 用verilog语言编程实现的SDRAM模块，可用于配置在FPGA中-Verilog language programming with the SDRAM module, can be used to configure the FPGA,
Sdram_Control_2Port
- 双端口SDRAM控制器，将SDRAM虚拟成两个端口，已经在ALTER DE2开发板的硬件上验证通过，采用Verilog HDL语言编写。-Dual-port SDRAM controller, SDRAM virtual into two ports, have ALTER DE2 development board hardware verification by using the Verilog HDL language.
FPGA_SDRAM
- FPGA对SDRAM的控制操作源码,用VERILOG硬件描述语言编写,包含的文件一共有:hostcont.v,inc.h,pinouts.ucf,sdram.v,top.v,tst_inc.h-Control of operation of the SDRAM FPGA source code, using VERILOG hardware descr iption language, the file contains a total of: hostcont.v, inc.h, pinout
SDRAMtest
- 使用quartus软件打开 内含sdram测试文件代码语言为verilog 备注清晰，适合初学者-Quartus software using open source test file containing sdram verilog Remarks clear language, suitable for beginners
SDRAM
- 基于SDRAM的存储器接口设计，采用verilog编写-SDRAM memory interface design based on
verilog
- verilog开发 sdram读写控制-verilog